发明名称 METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To realize electric inspection of a semiconductor integrated circuit having narrow-pitched test pads. SOLUTION: A semiconductor wafer is prepared, which is divided into a plurality of chip regions, has a semiconductor integrated circuit formed on each of the plurality of chip regions, and has a plurality of electrodes formed for being electrically connected with the semiconductor integrated circuit on a principal plane. A probe card having a plurality of contact terminals capable of contact with the plurality of electrodes is prepared. Meanwhile, a first sheet (2) is prepared, which includes the plurality of contact terminals (7) for being brought into contact with the plurality of electrodes, a second line electrically connected with the plurality of contact terminals and a first line, and an electric circuit formed in the vicinity of the plurality of contact terminals and composed of a passive element connected with the second line. Thereafter, the first sheet is attached to a wiring board so that a region where the plurality of contact terminals are formed can be pressed from the rear of the first sheet. COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2011064705(A) 申请公布日期 2011.03.31
申请号 JP20100280261 申请日期 2010.12.16
申请人 RENESAS ELECTRONICS CORP 发明人 OKAMOTO MASAYOSHI;MATSUMOTO HIDEYUKI;YORISAKI SHINGO;HASEBE AKIO;MOTOYAMA YASUHIRO;SHIMASE AKIRA
分类号 G01R1/073;H01L21/66 主分类号 G01R1/073
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