STACK CHIP PACKAGE

摘要

PURPOSE: A stack chip package is provided to reduce the number of a penetration silicon via passing through each chip by connecting a substrate and an upper chip module through a wire bonding. CONSTITUTION: In a stack chip package, a plurality of chips having a penetration silicon via(52) is laminated in a lower chip module through a conductive bump. A conducive flip-chip bonding(14) is connected between the bottom chip of the lower chip module and the conducive pattern of the substrate. A upper chip module(30) is laminated on the top chip of the lower chip module having a insulating material between them. A re-wiring(42) is interposed between the bonding pad of the top chip and the penetration silicon via A wire(16) electrically connects the bonding pad of the top chip of a upper chip module to the conductive pattern of a substrate.