发明名称 CACHE MEMORY SYSTEM AND CONTROL METHOD FOR WAY PREDICTION OF CACHE MEMORY
摘要 PROBLEM TO BE SOLVED: To provide a cache memory system and a control method for WAY prediction of a cache memory, which reduce failures of WAY prediction by WAY prediction not using address matching and is capable of preventing malfunction of the system. SOLUTION: A cache device 1 includes: a WAY information buffer 79 wherein WAY information being a selection result of WAY in an instruction which has accessed a cache memory 14 is stored; and a control circuit 80 which controls, during repeated execution of a series of instruction groups, storing processing for storing WAY information in the instruction groups into a WAY information buffer 79 and readout processing for reading out WAY information from the WAY information buffer 79. COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2011065503(A) 申请公布日期 2011.03.31
申请号 JP20090216570 申请日期 2009.09.18
申请人 RENESAS ELECTRONICS CORP 发明人 TAKAHASHI DAISUKE
分类号 G06F12/08 主分类号 G06F12/08
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