| 摘要 |
A method is provided for improving clock recovery signal jitter in digital communication based on a phase adjustment technique in a phase interpolation. A clock signal is expressed as the combination of two sinusoidal signals. The phase interpolating process determines the amplitude of the first sinusoidal signal, and the amplitude of the second sinusoidal signal that is 90° out of phase from the first sinusoidal signal. The clock signal is then formed by combining first sinusoidal signal with the second sinusoidal signal by choosing the first and second amplitude such that the amplitude of the clock signal is substantially a constant. Modulation of the clock signal amplitude is significantly improved by the disclosed technique over the conventional technique when the sum of the first and second amplitudes of the two sinusoidal functions is kept a constant.
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