发明名称 REFERENCE VOLTAGE CIRCUIT
摘要 PURPOSE: A reference voltage circuit is provided to suppress the change and curvature of the slope of a reference voltage to a temperature by generating the reference voltage through addition of the differential voltage of a threshold voltage in an enhancement NMOS transistor and the threshold voltage of a depression NMOS transistor. CONSTITUTION: In a reference voltage circuit, the gate of a first depression NMOS transistor(11) is connected to the gate of a second depression type NMOS transistor(12). The source of a second depression type NMOS transistor is connected to a second terminal. The drain of the first NMOS transistor(14) is connected to a first terminal. The source of the first NMOS transistor is connected to a ground terminal. The gate of the second NMOS transistor(15) is contacted with the drain, the gate of the first NMOS transistor, and a second terminal. The source of the second NMOS transistor is connected to the reference voltage output terminal. The second NMOS transistor has a threshold voltage lower than the that of the first NMOS transistor. The voltage generating circuit generates the reference voltage between the reference voltage output terminal and the ground terminal.
申请公布号 KR20110033795(A) 申请公布日期 2011.03.31
申请号 KR20100092325 申请日期 2010.09.20
申请人 SEIKO INSTRUMENTS INC. 发明人 YOSHINO HIDEO;IMURA TAKASHI
分类号 G05F3/24;G05F3/02 主分类号 G05F3/24
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