| 摘要 |
<p>A synchronous serial interface 3, e.g. a serial peripheral interface (SPI), for full duplex communication, comprises a clock line (CLK), a request line (REQN) and a ready line (RDYN) for handshake signals, a master-toÂ-slave data line (MOSI), and a slave-to-master data line (MISO). Master device 1 (e.g. a MCU) transmits a clock signal to slave device 2 (e.g. a radio transceiver) over the clock line. In a first transaction, the master sends a master transmission request over the request line and in response, the slave sends a slave transmission accept signal over the ready line, causing the master to transmit binary data over the MOSI line. In a second transaction, the slave sends a slave transmission request signal over the ready line; in response, the master sends a master transmission accept signal over the request line, causing the slave to transmit binary data over the MISO line. In at least one of the transactions, the master and slave transmit binary data at the same time as each other. In other embodiments, a slave transmits message-length information to the master and the master sends a transmission end signal.</p> |
