| 摘要 |
A voltage-to-digital converting device includes a first voltage-to-time converter outputting a first delay clock having a first time delay relative to a reference clock in response to an input voltage, and a second voltage-to-time converter outputting a second delay clock having a second time delay relative to the reference clock in response to a feedback voltage. The first and second time delays correspond respectively to the input and feedback voltages. A time-to-digital converting circuit receives the first and second delay clocks from the first and second voltage-to-time converters, compares phases of the first and second delay clocks, generates the feedback voltage based on result of phase comparison made thereby, and outputs a digital signal upon detecting that the phases of the first and second delay clocks are in-phase.
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