发明名称 Method for making a stacked package semiconductor module having packages stacked in a cavity in the module substrate
摘要 A stacked die chip scale package, in which a stacked die assembly is mounted within a cavity in a module substrate. In some embodiments certain of the die are stacked on a front side of a stacked die assembly substrate, and the stacked die assembly substrate is inverted in the cavity and the substrate is electrically interconnected to a front side of the module substrate; others of the die are stacked on the back side of the stacked die assembly substrate, and are interconnected by wire bonds to the front side of the module substrate. In some embodiments, the cavity is covered by a heat sink, and the stacked die assembly is mounted onto the heat sink. Also, methods for making the module are provided.
申请公布号 US7915084(B2) 申请公布日期 2011.03.29
申请号 US20100784434 申请日期 2010.05.20
申请人 STATS CHIPPAC LTD. 发明人 HONG SUNGMIN
分类号 H01L25/00;H01L23/12 主分类号 H01L25/00
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