| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a clock recovery circuit capable of reducing clock jitter and data reproduction circuit. <P>SOLUTION: A clock recovery circuit comprises: a sampler 13 for outputting sampling data obtained by sampling a serial input signal synchronously to a first clock signal; a phase comparator circuit 14 for outputting a serial phase information signal representing a phase relationship between the first clock signal and a clock of the serial input signal based on the sampling data; a serial/parallel converter circuit 17 for outputting a parallel phase information signal obtained by performing serial/parallel conversion on the serial phase information signal synchronously to a second clock signal; a digital filter circuit 16 for arithmetically operating a phase deviation signal and a phase delay/advance signal based on the parallel phase information signal; a phase control amount processing circuit 20 for outputting a phase control signal generated based on the phase deviation signal and the phase delay/advance signal synchronously to a third clock signal faster than the second clock signal; and a phase interpolation circuit 12 for outputting the first clock signal obtained by adjusting a phase of a reference clock signal inputted from the outside based on the phase control signal. <P>COPYRIGHT: (C)2011,JPO&INPIT |
