发明名称 DIGITAL PHASE LOCKED LOOP
摘要 PROBLEM TO BE SOLVED: To obtain a digital phase locked loop having a hold over function which suppresses an influence over temperature characteristics and aging during a hold over period, and maintains high stability of frequencies. SOLUTION: The digital phase locked loop has a temperature measurement means and a hold over means. The temperature measurement means measures temperature of the surroundings of a voltage control type clock oscillation means. During synchronization with an object for synchronization, the hold over means controls the clock oscillation means by output from a digital filter means, and calculates the output from the digital filter means, temperature in the surroundings of the clock oscillation means, and a two-dimensional polynomial which has elapsed time and the temperature in the surroundings of the clock oscillation means as terms from history of the elapsed time. During no synchronization with the object for synchronization, the hold over means estimates a control signal for controlling the clock oscillation means by the two-dimensional polynomial from the elapsed time after stopping synchronization with the object for synchronization and the temperature in the surroundings of the clock oscillation means, and controls the clock oscillation means by the estimated control signal. COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2011061421(A) 申请公布日期 2011.03.24
申请号 JP20090207967 申请日期 2009.09.09
申请人 MITSUBISHI ELECTRIC ENGINEERING CO LTD 发明人 FUKUNAGA SHINICHI
分类号 H03L7/14;H03L1/02 主分类号 H03L7/14
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