发明名称 MEMORY SYSTEM AND CONTROL METHOD FOR THE SAME
摘要 PURPOSE: A memory system and a control method for the same are provided to perform an LDPC decoding operation with high reliable data through one time processing operation. CONSTITUTION: A first ECC(Error-Correct Code) decoder(30) performs HDC(Hard Decision Code) decoding operation based on sector data, and a second ECC decoder(40) performs an LDPC(Low Density Parity Check) decoding operation based on frame data. A sector error flag section sets up a sector error flag which memorizes error data information of the HDC decoding operation. An ECC control section increases the reliability of sector data which do not include error data based on the information on the sector error flag section.
申请公布号 KR20110031092(A) 申请公布日期 2011.03.24
申请号 KR20100085836 申请日期 2010.09.02
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 SAKAUE KENJI;ISHIKAWA TATSUYUKI;ICHIKAWA KAZUHIRO
分类号 G06F11/10;G06F9/30 主分类号 G06F11/10
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