| 摘要 |
<P>PROBLEM TO BE SOLVED: To surely receive a signal transmitted in a serial format. <P>SOLUTION: A bit clock BCK has a positive edge for each bit of serial data DATA. A multiplication circuit 18 multiplies the bit clock BCK by N to generate a system clock PLLCK. A first counter 10 generates a timing signal S10 to be asserted every time counting the bit clock BCK M times. A shift register 12 receives serial data DATA and shifts one bit by one bit for every edge of the bit clock BCK. A latch circuit 16 synchronizes the data D1 of K bits from the shift register 12 with the timing signal S10 for latching. A second counter 20 generates a latch enable signal S12 to be asserted every time counting the system clock (M×N×J) times. <P>COPYRIGHT: (C)2011,JPO&INPIT |
