| 摘要 |
PROBLEM TO BE SOLVED: To accurately suppress speed variations caused by a comparatively small supply voltage, and to speedily suppress speed variations caused by a comparatively large power supply voltage. SOLUTION: A semiconductor integrated circuit includes first and second functional blocks MOD00, MOD01, a clock producing circuit PLL, and a clock supplying circuit CS0. First and second supply voltages VDD00, VDD01 whose voltage values are different form each other are supplied to the first and second functional blocks MOD00, MOD01. The MOD00 includes a first internal circuit BUF00 and a first logical circuit MFF00 capable of supplying one of the power supply voltage VDD01, and the MOD01 includes a second internal circuit BUF01 and a second logical circuit MFF01 capable of supplying the other of the supply voltage VDD00. The clock supply circuit CS0 includes a fine adjustment delay stage circuit FC0 and a rough adjustment delay stage circuit CC0, and a phase difference measuring circuit RSM0 while the RSM0 controls a delay time TF0 of the FC0 and a delay time TC0 of the CC0 according to a phase difference between first and second operation clock signals COUT00, COUT01. COPYRIGHT: (C)2011,JPO&INPIT
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