发明名称 |
Disposable Spacer Integration with Stress Memorization Technique and Silicon-Germanium |
摘要 |
An integrated process flow for forming an NMOS transistor (104) and an embedded SiGe (eSiGe) PMOS transistor (102) using a stress memorization technique (SMT) layer (126). The SMT layer (126) is deposited over both the NMOS transistor (104) and PMOS transistor (102). The portion of SMT layer (126) over PMOS transistor (102) is anisotropically etched to form spacers (128) without etching the portion of SMT layer (126) over NMOS transistor (104). Spacers (128) are used to align the SiGe recess etch and growth to form SiGe source/drain regions (132). The source/drain anneals are performed after etching the SMT layer (126) such that SMT layer (126) provides the desired stress to the NMOS transistor (104) without degrading PMOS transistor (102).
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申请公布号 |
US2011070703(A1) |
申请公布日期 |
2011.03.24 |
申请号 |
US20090549862 |
申请日期 |
2009.08.28 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
XIONG WEIZE;WU ZHIQIANG;WANG XIN |
分类号 |
H01L21/8238 |
主分类号 |
H01L21/8238 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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