发明名称 INTERRUPT ON/OFF MANAGEMENT APPARATUS AND METHOD FOR MULTI-CORE PROCESSOR
摘要 Provided are an interrupt on/off management apparatus and method for a multi-core processor having a plurality of central processing unit (CPU) cores. The interrupt on/off management apparatus manages the multi-core processor such that at least one of two or more CPU cores included in a target CPU set can execute an urgent interrupt. For example, the interrupt on/off management apparatus controls the movement of each CPU core from a critical section to a non-critical section such that at least one of the CPU cores is located in the non-critical section. The critical section may include an interrupt-disabled section or a kernel non-preemptible section, and the non-critical section may include an interrupt-enabled section or include both of the interrupt-enabled section and a kernel preemptible section.
申请公布号 US2011072180(A1) 申请公布日期 2011.03.24
申请号 US20100880335 申请日期 2010.09.13
申请人 发明人 LEE JU-PYUNG
分类号 G06F13/24 主分类号 G06F13/24
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