| 发明名称 |
SILICON DIE FLOORPLAN WITH APPLICATION TO HIGH-VOLTAGE FIELD EFFECT TRANSISTORS |
| 摘要 |
A floorplan for a die having three high-voltage transistors for power applications is described. The three high-voltage transistors are specifically placed in relation to each other to optimize operation.
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| 申请公布号 |
US2011068410(A1) |
申请公布日期 |
2011.03.24 |
| 申请号 |
US20100750248 |
申请日期 |
2010.03.30 |
| 申请人 |
GARNETT MARTIN E;HSING MICHAEL R |
发明人 |
GARNETT MARTIN E.;HSING MICHAEL R. |
| 分类号 |
H01L27/06 |
主分类号 |
H01L27/06 |
| 代理机构 |
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