发明名称 |
Method and apparatus for pipelined joint equalization and decoding for gigabit communications |
摘要 |
A method and apparatus for the implementation of reduced state sequence estimation is disclosed, with an increased throughput using precomputation (look-ahead), with only a linear increase in hardware complexity with respect to the look-ahead depth. The present invention limits the increase in hardware complexity by taking advantage of past decisions (or survivor symbols). The critical path of a conventional RSSE implementation is broken up into at least two smaller critical paths using pipeline registers. Various reduced state sequence estimation implementations are disclosed that employ one-step or multiple-step look-ahead techniques to process a signal received from a dispersive channel having a channel memory.
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申请公布号 |
US7913154(B2) |
申请公布日期 |
2011.03.22 |
申请号 |
US20080039474 |
申请日期 |
2008.02.28 |
申请人 |
AGERE SYSTEMS INC. |
发明人 |
AZADET KAMERAN;HARATSCH ERICH FRANZ |
分类号 |
H03M13/03;H04L25/03;H04L25/49 |
主分类号 |
H03M13/03 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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