发明名称 Scalable bus structure
摘要 A processing system is disclosed with a sending component and a receiving component connected by a bus. The bus may be configured with first and second channels. The sending component may be configured to broadcast on the first channel read and write address information, read and write control signals, and write data. The sending component may also be configured to signal the receiving component such that the receiving component can distinguish between the read and write address information, the read and write control signals, and the write data broadcast on the first channel. The receiving component may be configured to store the write data broadcast on the first channel based on the write address information and the write control signals, retrieve read data based on the read address information and the read control signals, and broadcast the retrieved read data on the second channel.
申请公布号 US7913021(B2) 申请公布日期 2011.03.22
申请号 US20060565041 申请日期 2006.11.30
申请人 QUALCOMM INCORPORATED 发明人 HOFMANN RICHARD GERARD;SCHAFFER MARK MICHAEL
分类号 G06F13/14;G06F13/00;G06F13/28;G06F13/40;G06F13/42 主分类号 G06F13/14
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