| 摘要 |
In a DDR memory controller, a clock control circuit is configured to output a clock signal selected from among a plurality of clock signals with different frequencies based on a frequency selection signal, to a DDR memory as an operation clock signal. A master DLL circuit is configured to receive one of the plurality of clock signals which has a maximum frequency as a reference clock signal to determine a delay code. A slave delay circuit is configured to delay a strobe signal from the DDR memory based on the determined delay code to generate an internal strobe signal for a data signal from the DDR memory.
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