发明名称 Integrated scheme for forming inter-poly dielectrics for non-volatile memory devices
摘要 Electronic devices and methods for forming electronic devices that allow for a reduction in device dimensions while also maintaining or reducing leakage current for non-volatile memory devices are provided. In one embodiment, a method of fabricating a non-volatile memory device is provided. The method comprises depositing a floating gate polysilicon layer on a substrate, forming a silicon oxide layer on the floating gate polysilicon layer, depositing a first silicon oxynitride layer on the silicon oxide layer, depositing a high-k dielectric material layer on the first silicon oxynitride layer, depositing a second silicon oxynitride on the high-k dielectric material, and forming a control gate polysilicon layer on the second silicon oxynitride layer. In one embodiment, the high-k dielectric material layer comprises hafnium silicon oxynitride.
申请公布号 US7910446(B2) 申请公布日期 2011.03.22
申请号 US20080163542 申请日期 2008.06.27
申请人 APPLIED MATERIALS, INC. 发明人 MA YI;KHER SHREYAS;AHMED KHALED
分类号 H01L21/336 主分类号 H01L21/336
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