| 摘要 |
A exemplary aspect of the present invention is a simulation method for a semiconductor circuit that includes: a well resistor comprising a terminal region and a main body; and a plurality of contacts formed above the terminal region, the simulation method comprising: modeling a parasitic resistance Rt0 of the terminal region between the plurality of contacts and the main body by the following formula, where &rgr;0, L′0, W′0 are fitting parameters; L′ is a length of the terminal region in the longitudinal direction of the well resistor; and W′ is a width of the terminal region in the width direction of the well resistor. Rt 0 = &rgr; 0 × ( L ′ + L 0 ′ ) L ′ × ( W ′ + W 0 ′ )
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