| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device that reduces current consumption and performs stable set/reset operation. <P>SOLUTION: A memory cell array 1 formed of an array of memory cells MC each located between a word line WL and a bit line BL, and each including a variable resistor VR. A current mirror circuit 2b in a column control circuit 2 limits a current flowing through the bit lines BL to a predetermined upper limit Icomp or less. When a write operation or an erase operation on the memory cells MC is repeated a plurality of times, the current mirror circuit 2b sets the upper limit Icomp in the p-th write or erase operation higher than the upper limit Icomp in the q-th (q<p) write or erase operation. <P>COPYRIGHT: (C)2011,JPO&INPIT</p> |
