| 摘要 |
A memory cell includes a pair of magnetic tunnel junctions and a pair of associated transistors. The magnetic tunnel junctions of the pair are differentially disposed so that in response to the applied voltages, when one them stores a logic one, the other one stores a logic zero. Accordingly, the read operation margin is increased by a factor of two. The true and complementary bit lines of the differential memory cell are coupled to a sense amplifier. Consequently, the need for using reference bit lines is eliminated.
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