TEST PATTERN GENERATION METHOD, TEST PATTERN GENERATION DEVICE, FAILURE INSPECTION METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT, AND FAILURE INSPECTION DEVICE FOR SEMICONDUCTOR INTEGRATED CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide a test pattern generation device for automatically generating a test pattern without using a test pattern generation method and device related to an ATPG. SOLUTION: The test pattern generation method includes a property generation step for outputting a property that describes an operation of a circuit based on circuit information and failure information of a detection object in the circuit, and a format verification step for outputting a test pattern of the circuit based on the property. COPYRIGHT: (C)2011,JPO&INPIT