发明名称 SYSTEMS AND METHODS FOR REDUCING MEMORY ARRAY LEAKAGE IN HIGH CAPACITY MEMORIES BY SELECTIVE BIASING
摘要 <p>A source-biasing mechanism for leakage reduction in SRAM in which SRAM cells are arranged into a plurality of sectors. In standby mode, the SRAM cells in a sector in the plurality of sectors are deselected and a source-biasing potential is provided to the SRAM cells of the plurality sectors. In working mode, the source-biasing potential provided to the SRAM cells of a selected sector in the plurality of sectors is deactivated and the SRAM cells in a physical row within the selected sector are read while the remaining SRAM cells in the unselected sectors continue to be source-biased. The source-biasing potential provided to the SRAM cells that are in standby mode can be set to different voltages based on the logical state of control signals.</p>
申请公布号 WO2011032151(A1) 申请公布日期 2011.03.17
申请号 WO2010US48785 申请日期 2010.09.14
申请人 VIRAGE LOGIC CORP.;BEHERA, NIRANJAN;SABHARWAL, DEEPAK;ZHANG, YONG 发明人 BEHERA, NIRANJAN;SABHARWAL, DEEPAK;ZHANG, YONG
分类号 G11C11/412;G11C11/413 主分类号 G11C11/412
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