发明名称 |
DRAM CELL UTILIZING A DOUBLY GATED VERTICAL CHANNEL |
摘要 |
A double-gate vertical channel transistor (DGVC) structure is described which is particularly well suited for Dynamic RAM (DRAM) memory (e.g., capacitorless DRAM) wherein the memory cell occupies a small cell area of 4F2, and provides beneficial retention properties including immunity to disturbances. The vertical transistors are arranged in an alternating gate-facing orientation, with a common source formed on a first end and separate drains on their second ends. Word lines comprise alternating front gates and back gates shared by columns of gate-facing transistors on each side of it. The DGVC cell provides enhanced scalability allowing the continued scaling of DRAM technology and can be fabricated using low-cost semiconductor materials and existing fabrication techniques. Fabrication techniques and array biasing are also described for the DGVC cell arrays. |
申请公布号 |
WO2011031749(A2) |
申请公布日期 |
2011.03.17 |
申请号 |
WO2010US48116 |
申请日期 |
2010.09.08 |
申请人 |
THE REGENTS OF THE UNIVERSITY OF CALIFORNIA;KWON, WOOKHYUN;LIU, TSU-JAE, KING |
发明人 |
KWON, WOOKHYUN;LIU, TSU-JAE, KING |
分类号 |
H01L27/108;H01L21/335;H01L21/8242;H01L29/78 |
主分类号 |
H01L27/108 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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