DEFECT INSPECTION PATTERN CIRCUIT, SEMICONDUCTOR WAFER AND METHOD OF INSPECTING DEFECT

摘要

PROBLEM TO BE SOLVED: To enable a defect inspection pattern circuit to detect a defective contact for both a p-side contact and an n-side contact. SOLUTION: The defect inspection pattern circuit includes a p-type semiconductor substrate 1, at least two p-type well regions 2, 4, at least one n-type well region 3, a first p+-type active region 6 provided in one of the p-type well regions, an n+-type active region 8 provided in the other p-type well region 4, a second p+-type active region 7 provided in the n-type well region 3, a contact plug 10 provided in the first p+-type active region 6, pairs of contact plugs 12, 13, each being provided in the n+-type active region 8 and the second p+-type active region 7, respectively, and interconnections 15, 16, 17 for forming a contact chain, by connecting the contact plugs in the upper and lower layers to each other, starting from the contact plug 10 provided in the first p+-type active region 6. The volume of the n-type well region 3 is made smaller than that of the p-type well region 2 where the first p+-type active region 6 is formed. COPYRIGHT: (C)2011,JPO&INPIT