发明名称 |
System with dual rail regulated locked loop |
摘要 |
<p>The invention relates to an apparatus comprising a plurality of delay elements to generate a plurality of incrementally delayed clock signals wherein at least one of the delayed clock signals swings between an upper supply voltage and a lower supply voltage; and a voltage control circuit coupled to provide the upper supply voltage and the lower supply voltage to each of the delay elements, the voltage control circuit configured to adjust the upper supply voltage and the lower supply voltage according to a phase difference between a selected pair of the delayed clock signals.</p> |
申请公布号 |
EP2296276(A2) |
申请公布日期 |
2011.03.16 |
申请号 |
EP20100183041 |
申请日期 |
2003.03.20 |
申请人 |
RAMBUS INC. |
发明人 |
KIZER, JADE M.;LAU, BENEDICT C.;HAMPEL, CRAIG E. |
分类号 |
H03L7/00;G06F1/10;H03K5/13;H03L7/07;H03L7/081 |
主分类号 |
H03L7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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