| 摘要 |
A method and apparatus of interleaving memory banks in a multi-layer bus system. The apparatus includes a plurality of slave interface units receiving signals requesting a bus access and generating control signals, and a controller receiving the control signals generated from the plurality of slave interface units and generating signals required to access the memory banks. Accordingly, it is possible to greatly reduce a delay time caused when accessing a synchronous dynamic random access memory (SDRAM), for example, in a multi-layer bus system. |
