发明名称 |
Memory controller and method for optimized read/modify/write performance |
摘要 |
A memory controller optimizes execution of a read/modify/write command by breaking the RMW command into separate and unique read and write commands that do not need to be executed together, but just need to be executed in the proper sequence. The most preferred embodiments use a separate RMW queue in the controller in conjunction with the read queue and write queue. In other embodiments, the controller places the read and write portions of the RMW into the read and write queue, but where the write queue has a dependency indicator associated with the RMW write command in the write queue to insure the controller maintains the proper execution sequence. The embodiments allow the memory controller to translate RMW commands into read and write commands with the proper sequence of execution to preserve data coherency.
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申请公布号 |
US7908443(B2) |
申请公布日期 |
2011.03.15 |
申请号 |
US20080136750 |
申请日期 |
2008.06.10 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
HILLIER, III PHILIP ROGERS;HOVIS WILLIAM PAUL;KIRSCHT JOSEPH ALLEN |
分类号 |
G06F12/00 |
主分类号 |
G06F12/00 |
代理机构 |
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