| 摘要 |
A switched capacitor measurement circuit is provided for measuring the capacitance of an input capacitor with a parallel parasitic resistor. The circuit comprises a switching arrangement, a reference capacitor, a steered current sink and an operational amplifier with an output, a non-inverting input connected to a reference voltage source and an inverting input connected to a first terminal of the input capacitor. The current sink is steered to compensate for a charge current due to the parasitic resistor. Still further, the circuit comprises a digital adder and an analog-to-digital converter with an analog input connected to the output of the operational amplifier and a digital output connected to a first input of the digital adder. A second input of the digital adder receives a negative digital error signal and the output of the digital adder provides a digital capacitance measurement signal corrected for an error current which is integrated across the reference capacitor in the gain mode due to the slewing of the operational amplifier.
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