发明名称 RECEIVING APPARATUS AND RECEIVING METHOD THEREOF
摘要 The receiving apparatus according to the present invention includes a multi-phase clock generating circuit, a latch component, an error check component, and a selector circuit. The multi-phase clock generating circuit generates a plurality of clocks, phases of which are different from each other. The latch component receives an external data divided into two or more and the plurality of the clocks, and concurrently obtains a plurality of data, clock-timing of which is different from each other, by latching the external data by different clocks. The error check component detects an error of the respective data. The selector circuit selects data judged as no-error data from the plurality of the data, and outputs the selected data as received data. According to the circuit configuration like this, it is possible to precisely receive the data.
申请公布号 US2011057691(A1) 申请公布日期 2011.03.10
申请号 US20100874682 申请日期 2010.09.02
申请人 RENESAS ELECTRONICS CORPORATION 发明人 HIRASHIMA YASUHIRO
分类号 H03L7/00 主分类号 H03L7/00
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