发明名称 |
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE |
摘要 |
A sub-decoder element provided corresponding to each word line is constructed by the same conductive type MOS transistors. The sub-decoder elements are arranged in a plurality of columns such that the layout of active regions for forming the sub-decoder elements is inverted in a Y direction and displaced by one sub-decoder element in an X direction. The arrangement of the sub-decoder elements is adjusted such that high voltage is not applied to both of gate electrodes adjacent in the Y direction. A well voltage of a well region for forming the sub-decoder element group is set to a voltage level such that a source to substrate of the transistor of the sub-decoder element is set into a deep reversed-bias state. In a nonvolatile semiconductor memory device, the leakage by a parasitic MOS in a sub-decoder circuit or word line driving circuit to which a positive or negative high voltage is supplied, can be suppressed.
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申请公布号 |
US2011058426(A1) |
申请公布日期 |
2011.03.10 |
申请号 |
US20100944358 |
申请日期 |
2010.11.11 |
申请人 |
RENESAS ELECTRONICS CORPORATION |
发明人 |
KUSAKABE YOSHIHIKO;OTO KENICHI;KAWASAKI SATOSHI |
分类号 |
G11C16/06 |
主分类号 |
G11C16/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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