发明名称 Tiling Compaction in Multi-Processor Systems
摘要 A method and system for processing a graphics frame in a multi-processor computing environment are described. Embodiments of the present invention enable the reduction of the memory footprint required for processing a graphics frame in a multi-processor system. In one embodiment a method of processing a graphics frame using a plurality of processors is presented. The method includes determining a respective assignment of tiles of the graphics frame to each processor of the plurality of processors; allocating a memory area in a local memory of each processor, where the size of the allocated memory area substantially corresponds to the aggregate size of tiles assigned to the respective processor; and storing the tiles of the respective assignment of tiles in the memory area of each respective processor.
申请公布号 US2011057935(A1) 申请公布日期 2011.03.10
申请号 US20100879582 申请日期 2010.09.10
申请人 FOWLER MARK 发明人 FOWLER MARK
分类号 G06F15/16 主分类号 G06F15/16
代理机构 代理人
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