| 摘要 |
In an embodiment, a semiconductor memory device including a cell array with NAND strings arranged therein, wherein the device has such a program mode that bit lines and cell's channels of the NAND strings coupled thereto are initially charged in accordance with program data, and then program voltage is applied to memory cells selected in the cell array. In the program mode, a certain bit line and a program-inhibited cell's channel coupled thereto, which are initially charged to Vdd, are boosted to be higher than Vdd by capacitive coupling from the cell source line prior to the program voltage application.
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