| 摘要 |
To include an AL counter that outputs a second ODT signal after counting a clock signal by an additive latency after receiving a first ODT signal, and a counter control circuit that controls the AL counter such that the second ODT signal having the same logic value as a logic value of the first ODT signal at a time of shifting from an asynchronous mode to a synchronous mode is output during a period until when at least the clock signal is input by an additive latency after the shifting. With this configuration, an interruption of an CDT operation can be prevented without separately providing a CKE counter. Therefore, the circuit scale can be reduced and the power consumption can be also reduced.
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