发明名称 DELAY LOCK LOOP CIRCUIT AND SEMICONDUCTOR INTEGRATION CIRCUIT DEVICE
摘要 <P>PROBLEM TO BE SOLVED: To provide a delay lock loop circuit with a smaller circuit area and a semiconductor integration circuit device installed with the delay lock loop circuit, which address a wide frequency band from a low frequency to a high frequency. <P>SOLUTION: A delay lock loop circuit includes a phase change circuit, a delay line circuit and delay control circuit. The phase change circuit outputs a first signal having a first phase difference with respect to a reference clock inputted therein and a second signal having a second phase difference. A difference between the first and second phase differences shows a predetermined amount of phase delay. The delay line circuit includes a plurality of delay circuits each having a variable unit amount of delay. The delay control circuit controls the unit amount of delay in order for a sum of the unit amounts of delay to be equal to a reference amount of phase delay. <P>COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2011049790(A) 申请公布日期 2011.03.10
申请号 JP20090196083 申请日期 2009.08.26
申请人 RENESAS ELECTRONICS CORP 发明人 SHIHARA MASAHIKO;TANGODEN ATSUSHI
分类号 H03L7/081;H03K5/131;H03K5/14;H03L7/00 主分类号 H03L7/081
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