发明名称 Digital signal coding apparatus, digital signal decoding apparatus, digital signal arithmetic coding method and digital signal arithmetic decoding method
摘要 In a bit stream syntax containing compressed video slice data for compressed video data of a slice structure, a slice header for compressed video slice data has attached thereto a slice start code, a register reset flag indicating whether a register value, which designates a status of a codeword occurring in an arithmetic coding process, should be reset, an initial register value which indicates a register value to be used to start arithmetic coding, only when the register reset flag indicates that the register should not be reset and information indicating the context model status of the preceding slice.
申请公布号 EP2293450(A1) 申请公布日期 2011.03.09
申请号 EP20100011914 申请日期 2003.04.10
申请人 MITSUBISHI DENKI K.K. 发明人 SEKIGUCHI, SHUNICHI;YAMADA, YOSHIHISA;ASAI, KOHTARO
分类号 H03M7/40;G06T9/00;H04N7/24;H04N7/52;H04N19/00;H04N19/105;H04N19/13;H04N19/174;H04N19/46;H04N19/51;H04N19/625;H04N19/70;H04N19/91 主分类号 H03M7/40
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