SIMULATION METHOD FOR INTEGRATED CIRCUIT

摘要

PURPOSE: A simulation method for integrated circuit is provided to reduce the operation time by combining static timing analysis while maintaining the exactness of the event driving method. CONSTITUTION: A layout of an IC(Integrated Circuit) is divided into a clock network, and a non clock network(120). A delay value from a source to a flip-flop is calculated and stored using a static timing analysis(130). An IC is simulated using an event driven mode(140). The event generated between the source and the flip-flop is not generated, but analyzed using the stored delay value. The periodic signal is a clock signal, and the source is the clock source.