| 摘要 |
A comparator for a pipelined ADC includes a sampling circuit coupled to a plurality of differential input voltages and a plurality of differential reference voltages, for sampling the plurality of differential input voltages according to a first clock signal and sampling the plurality of differential reference voltages according to a second clock signal, a preamplifier coupled to the sampling circuit comprising a positive input terminal, a negative input terminal, a positive output terminal, and a negative output terminal, for amplifying a voltage across the positive input terminal and the negative input terminal for generating a plurality of differential output voltages, and a latch circuit coupled to the preamplifier for latching the plurality of differential output voltages.
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