发明名称 |
Processor system using synchronous dynamic memory |
摘要 |
A processor system including: a processor and controller core connected via an internal bus; and a plurality of synchronous memory chips connected to the processor via an external bus; the controller core including a mode register selected by an address signal from the processor core and written with an information by a data signal from the processor core to select the operation mode of the plurality of synchronous memory chips, and a control unit to prescribe the operate mode to the plurality of synchronous memory chips based on the information written in the mode register, wherein the controller core outputs a mode setting signal based on the information written in the mode register or an access address signal from the processor core to the plurality of synchronous memory chips via the external bus selectively; and wherein the clock signal is commonly supplied to the plurality of synchronous memory chips.
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申请公布号 |
US7904641(B2) |
申请公布日期 |
2011.03.08 |
申请号 |
US20080123195 |
申请日期 |
2008.05.19 |
申请人 |
RENESAS TECHNOLOGY CORPORATION |
发明人 |
UCHIYAMA KUNIO;NISHII OSAMU |
分类号 |
G06F12/00;G06F15/78;G11C7/10;G11C8/12;G11C8/18;H04N7/26;H04N7/50 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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