发明名称 |
Method and system for implementing parallel processing of electronic design automation tools |
摘要 |
Disclosed is an improved method and system for processing the tasks performed by an EDA tool in parallel. The IC layout is divided into a plurality of layout windows and one or more of the layout windows are processed in parallel. Sampling of one or more windows may be performed to provide dynamic performance estimation.
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申请公布号 |
US7904852(B1) |
申请公布日期 |
2011.03.08 |
申请号 |
US20050225853 |
申请日期 |
2005.09.12 |
申请人 |
CADENCE DESIGN SYSTEMS, INC. |
发明人 |
CADOURI EITAN;KOZMINSKI KRZYSZTOF A.;LIAO HAIFANG;MEDNICK KENNETH;RUEHL ROLAND;SNOWDEN MARK A. |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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