发明名称 |
Decoding apparatus and method |
摘要 |
A decoding apparatus is disclosed. The decoding apparatus is applied to a data signal comprising a plurality of bits. A plurality of sampled data is generated by sampling the data signal. Each of the bits has a same cycle. The decoding apparatus comprises a calculating module and a determining module. When the calculating module sets a first interval and a second interval in the cycle of a specific bit, the calculating module generates a first count according to the sampled data in the first interval corresponding to a first logic level and generates a second count according to the sampled data in the second interval corresponding to a second logic level. The determining module determines a digital logic value of the specific bit.
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申请公布号 |
US7903004(B2) |
申请公布日期 |
2011.03.08 |
申请号 |
US20090542777 |
申请日期 |
2009.08.18 |
申请人 |
MSTAR SEMICONDUCTOR, INC. |
发明人 |
CHANG CHIUNG HUNG;CHIANG YING-CHIEH |
分类号 |
H03M7/40 |
主分类号 |
H03M7/40 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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