发明名称 |
Configuration of gate to drain (GD) clamp and ESD protection circuit for power device breakdown protection |
摘要 |
A semiconductor power device supported on a semiconductor substrate comprising a plurality of transistor cells each having a source and a drain with a gate to control an electric current transmitted between the source and the drain. The semiconductor further includes a gate-to-drain (GD) clamp termination connected in series between the gate and the drain further includes a plurality of back-to-back polysilicon diodes connected in series to a silicon diode includes parallel doped columns in the semiconductor substrate wherein the parallel doped columns having a predefined gap. The doped columns further include a U-shaped bend column connect together the ends of parallel doped columns with a deep doped well disposed below and engulfing the U-shaped bend.
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申请公布号 |
US7902604(B2) |
申请公布日期 |
2011.03.08 |
申请号 |
US20090378039 |
申请日期 |
2009.02.09 |
申请人 |
ALPHA & OMEGA SEMICONDUCTOR, INC. |
发明人 |
SU YI;BHALLA ANUP;NG DANIEL |
分类号 |
H01L23/62 |
主分类号 |
H01L23/62 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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