LATENCY CIRCUIT FOR GENERATING LATENCY SIGNAL USING 1-DIVISION OR 2-DIVISION METHOD AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME

摘要

PURPOSE: A latency circuit for generating latency signal using 1-division or 2-division method and a semiconductor memory device having the same are provided to improve noise feature of a delay duplication circuit by reducing the number of delay unit in a delay duplication circuit. CONSTITUTION: A latency control clock generator(120) generates a signal having a frequency which is formed by dividing an original frequency by m. A latency control clock generator generates at least one latency control clock. The latency signal generating unit(130) generates a latency signal. The latency control clock generator is comprised of a delay locked loop(121), a clock divider(122), a delay locked loop duplicating unit(123), and an internal read command signal generation duplication unit(124). A delay locked loop generates an in-phase signal. A clock divider divides the in-phase signal by 2 The delay locked loop duplication unit generates an output signal which is synchronized with the external clock. The internal read command signal generation duplication unit generates the latency control clock.