| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To suppress increase of the number of row decoders even if the number of memory planes in a chip increases. <P>SOLUTION: The NAND type flash memory includes: a first transfer transistor 18 disposed between first and second memory planes 11A and 11B and commonly connected to first word lines WL0 to WLn in a first NAND block BKi and second word lines WL0 to WLn in a third NAND block BKi; a second transfer transistor 18 disposed at a first end of the first memory plane 11A opposite the second memory plane 11B and connected to third word lines WL0 to WLn in a second NAND block BK(i+1); and a third transfer transistor 18 disposed at a second end of the second memory plane 11B opposite the first memory plane 11A and connected to fourth word lines WL0 to WLn in a fourth NAND block BK(i+1). <P>COPYRIGHT: (C)2011,JPO&INPIT</p> |
