WAFER LEVEL CHIP SCALE PACKAGE AND METHOD FOR FABRICATING THE SAME

摘要

PURPOSE: A wafer level chip scale package and a method for fabricating the same are provided to prevent a pattern defect due to plating which is generated in a rewiring and a rewiring pad at the same time by forming a rewiring and a rewiring pad through an additional process. CONSTITUTION: In a wafer level chip scale package and a method for fabricating the same, a bonding pad is formed on the top of a semiconductor chip(20). A first insulating layer(23) is formed on the top of the semiconductor chip. A rewiring pad(25) is spaced from the boding pad and is formed in the first insulating layer. A surface plating layer(26) is formed on the top and side of the rewiring pad. A rewiring line(27) electrically connects the bonding pad and the rewiring pad.