发明名称 TRANSACTIONAL MEMORY SYSTEM WITH EFFICIENT CACHE SUPPORT
摘要 <p>A computer implemented method for use by a transaction program for managing memory access to a shared memory location for transaction data of a first thread, the shared memory location being accessible by the first thread and a second thread. A string of instructions to complete a transaction of the first thread are executed, beginning with one instruction of the string of instructions. It is determined whether the one instruction is part of an active atomic instruction group (AIG) of instructions associated with the transaction of the first thread. A cache structure and a transaction table which together provide for entries in an active mode for the AIG are located if the one instruction is part of an active AIG. The next instruction is executed under a normal execution mode in response to determining that the one instruction is not part of an active AIG.</p>
申请公布号 WO2011023679(A1) 申请公布日期 2011.03.03
申请号 WO2010EP62302 申请日期 2010.08.24
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION;IBM UNITED KINGDOM LIMITED;HELLER, THOMAS, JR. 发明人 HELLER, THOMAS, JR.
分类号 G06F9/46 主分类号 G06F9/46
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