Method and apparatus for operation of a NAND-like dual charge retaining transistor NOR flash memory device

摘要

A method and apparatus for operation for the NAND-like dual charge retaining transistor NOR flash memory cells begins by erasing, verifying over-erasing the threshold voltage level of the erased charge retaining transistors to an erased threshold voltage level. Then method progresses by programming one of two charge retaining transistors of the NAND-like dual charge retaining transistor NOR flash memory cells to a first programmed threshold voltage level, and programming the other of the two charge retaining transistors of the NAND-like dual charge retaining transistor NOR flash memory cells to the first programmed threshold voltage level or to a second programmed threshold voltage level. Combinations of the erased threshold voltage level and the first and second programmed threshold voltage levels determine an internal data state of the NAND-like dual charge retaining transistor NOR flash memory cells which are then decoded to ascertain the external data logical state.