DIRECT SAMPLING CIRCUIT AND RECEIVER

摘要

Disclosed are a direct sampling circuit and a receiver wherein an excellent frequency characteristic is achieved by use of a relatively simple structure and simple clocks. In each of a plurality of discrete-time circuits (102-1 to 102-4), a charging switch (1021) is on/off controlled by use of one of four-phase control signals. A rotate capacitor (1022) shares, via the charging switch (1021), a charge stored in an IQ generating circuit (101). A dump switch (1023) is on/off controlled by use of another one of the four-phase control signals the phase of which is different from that of the control signal used to on/off control the charging switch (1021). A buffer capacitor (1026) shares, via the dump switch (1023), a charge with the rotate capacitor (1022), thereby forming an output value.